DFT Verification Engineer - San Jose, CA
San Jose, CA
Full Time Position
Understand basic DFT technologies such as SCAN / ATPG, MBIST, JTAG.
Experience on ATPG tools (Mentor TK or Synopsys Tmax) and scan insertion tools (DC).
Experience on ATPG pattern generation, test coverage debug, RTL and gate level simulations.
Understand Verilog, Perl or TCL script languages.
Responsible for JTAG & MBIST implementation and verification.
Responsible for SCAN insertion and DRC analysis/debug.
Responsible for achieving high SCAN coverage and low DPPM.
Responsible for SCAN, MBIST and JTAG gate-level simulations.
Responsible for ATPG vector generation and ATE debug.
Contribute to overall DFT methodology/tooling for 16/7nm flow.
Contribute to SoC DFT SCAN, MBIST and JTAG architecture.
Contribute to SCAN, MBIST and JTAG timing constraints/analysis.
Strong understanding of DFT methodologies and tooling.
DFT experience on SoCs with multiple scan chains and clocks.
SCAN chain implementation at chip and block level.
MBIST implementation at chip and block level.
JTAG implementation at chip level.
Understanding of test compression and ATE debug.
Gate simulation setup and debug.
Test mode timing constraint development and analysis is a plus.
DFT architecture experience is a plus.