DFT Engineer (ATPG, GLS)

Santa Clara, California, United States

Description

DFT Engineer

santa clara , CA

Fixed Term Employment


Job Description:

Use SpyglassDFT to ensure RTL or netlist can achieve world class ATPG coverage

Run and debug DRC on designs at 0.5, 0.8 and 1.0 milestone

Develop scan_waivers.tcl and dfx_setup.tcl as handoff from RTL to Synthesis

Raise bugs and follow through the bug closure process in HSD until it is disposition

Use Synopsys DFTC to generate scan inserted netlist

Run and debug DRC on Intel designs at 0.5, 0.8 and 1.0 milestone to generate scan inserted netlist

Review DRC report to make sure all failures are clean and understood with engineers

Update scan_waivers.tcl and dfx_setup.tcl if necessary

Review of scan insertion and coverage point are world class with engineers

Raise bugs and follow through the bug closure process in HSD until it is disposition.

Use Mentor to ATPG and generate testbench

Run and debug DRC on Intel designs at 0.5, 0.8 and 1.0 milestone

Do low scan coverage debug and update scan waivers.tcl and dfx_setup.tcl if neccesary

Raise bugs and follow through the bug closure process in HSD until it is disposition

Generate test benches for GLS

Joint review with engineers and updates

Use VCS to GLS

Run and debug GLS failure on designs at 0.5, 0.8 and 1.0 milestone

Raise bugs and follow through the bug closure process in HSD until it is disposition

Develop and revision control GLS error free ATPG Ward and ASCII patterns as hand-off to post-silicon team

Joint review of GLS results with engineers.

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