Design Verification Engineer

Folsom, California, United States

Description

Design Verification Engineer

Folsom, CA

Full Time Position

Job Description:

In depth knowledge/experience of System Verilog OVM/UVM.

Experience & good understanding of asic/fpga pre-silicon verification concept i.e. focus vs full/constraint random testing, coverage based verification.

Experience in coverage points coding, SV test writing & debug, testbenching.

Familiar with unix/linux environment

Experience with network protocols desired

Willingness and commitment to work in a process driven environment and contribute to process improvement

Good communication and interpersonal skills to work with different teams

Soft skills:

Good communication and written skills

Team player

Self-motivated

Good Customer Service skills

Ability to document processes, solutions, issues and risks


Thanks

Macropace

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