Design &verification Engineer
Design& Verification Enginneer
Folsom , CA
Full time position
its an immediate requirement from the client side clients wants to close this position ASAP
for this position we have some good budget As of now let me know on that for this position we have full time benefits as well
In depth knowledge/experience of System Verilog OVM/UVM.
Experience & good understanding of asic/fpga pre-silicon verification concept i.e. focus vs full/constraint random testing, coverage based verification.
Experience in coverage points coding, SV test writing & debug, testbenching.
Familiar with unix/linux environment
Experience with network protocols desired
clients are particular looking about verilog , ASIc, FPGA, UVM,