Emulation Engineer - Folsom, CA
Full Time Position
Your responsibility will be to write and debug manufacturing feature tests for SoC ICs as modeled in emulation.
Candidates must have experience performing ASIC - Verification based on architectural/micro-architectural specification review and analysis followed with the definition of Verification requirements.
Develop tests and test bench components from high-level Verification plans, as well as debug of failing tests, the definition of functional coverage space, implementation of coverage monitors and analysis of test coverage space, regression running and debugging failing tests, design and development of test bench collateral.
Building gate-level emulation models to support post-scan-inserted-netlist validation for functional and ATPG on emulation platform
System Verilog, Verilog, C/C++ programming, Computer architecture, Verification experience using simulation and emulation.
Nice to Have:
Good in Python/Perl, Git
Strong Platform/SoC software/hardware debug skills;
Good communication and planning skills
Must be self-motivated, self-starter, and eager to take on new challenges.
Bachelor Degree in Computer Science or equivalent stream