Static Timing Analysis / Synthesis Engineer
Client: CMMi Level 5 Company
Exp: 4-10 Yrs
Job Description: Static Timing Analysis / Synthesis Engineer
- · Responsibilities: · Synthesizing the multi-power domain blocks/IPs with challenging power, area and timing constraints · Formal Equivalence Checking · Constraint development, timing closure and STA · Support to physical design team in fine-tuning the floorplan & constraints for implementation. · UPF/CPF based flow. Desired Skills: · Must posses 6-10 years of experience working in low power design synthesis, preferably using UPF. · Working knowledge of Physical Design implementation for a block · Proficient in using SYNOPSYS technologies, DC,PT · Technologies: 14nm,16nm,20nm · Experience in TCL/Perl is a plus · Excellent verbal and written communication skills · Excellent interpersonal and analytical skills with the ability to work independently and work with physical designers to close the feedback loop.