ASIC verification Engineer

San Jose, California, United States

Description

ASIC verification Engineer

San Jose, CA

Full Time Position


- Develop and enhance scoreboard checks and stimulus
- Develop directed and random verification ntests to validate block and IP functionality
- Develop verification function coverage
- HDL Code coverage analysis and run gate sim
- Debug regression failures

Required skills:
- 5 or more years of proven verification experience on large ASIC development projects
- Hands on design verification experience with high-speed transceiver protocols, Memory controller, Ethernet, Serdes (one of them) is a must
- Strong background in SystemVerilog and UVM verification methodologies
- Expertise in C/C++, Verilog, System Verilog, System C, Python, UVM etc.
- Strong debug skills and experience with debug tools such as DVE/Verdi
- Strong analytical/problem solving skills and pronounced attention to details
- Strong interpersonal and communication skills

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