Design Verification Engineer (Soc, RTL):

Santa Clara, California, United States


Design Verification Engineer (Soc, RTL):

Santa Clara CA

Fulltime Position

Job Description:

5+ years of Design verification experience in building and architecting Cluster/SoC verification environments,

preferably from scratch for multiple projects.

The engineer should have experience in writing test plan, creating & enhancing verification environments

and be comfortable coding any portion of a test bench (models, checkers, scoreboards, coverage monitors etc.).


Languages: Must have experience in Verilog/SystemVerilog.

Methodology: Strong UVM experience is a must.

Experience with cluster level/SoC RTL & gate level simulation( unit-delay, with sdf for timing) and debug is highly desirable.

Working knowledge of AXI/AHB/APB protocol.

DV experience with peripherals such as PCIe,CSI-2,MIPI-D PHY are highly desirable.

Strong understanding of Functional Coverage and Assertions.

Experience in working with VIPs like PCIe, AMBA is a plus

Experience in Perl/shell scripting is a plus.

Understanding entire ASIC verification flow from spec to Tapeout.

Good interpersonal/communication skill.

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