Design Verification Engineer - Folsom, CA
Design Verification Engineer
Full Time Position
In depth knowledge/experience of System Verilog OVM / UVM.
Experience & good understanding of ASIC / FPGA Pre-Silicon verification concept i.e. focus vs full/constraint random testing, coverage based verification.
Experience in coverage points coding, SV test writing & debug, testbenching.
Familiar with Unix / Linux environment
Experience with network protocols desired
Nice to Have:
Good in Python / Perl
Strong Platform / SoC Software / Hardware Debug skills
Good communication and planning skills
Must be self-motivated, self-starter, and eager to take on new challenges.Bachelor Degree in Computer Science or equivalent stream