System Level Verification- Mountain View, CA

Mountain View, California, United States


System Level Verification Engineer

Mountain View, CA

Full Time Position

Job Description:

Verilog and C/C++ coding a must

Makefiles, Perl scripting a must

Chip/full system level ASIC Verification skills, and debug skills a must

Debug using waveforms a must, Verdi source level debug a plus

Board level debug with logic analyzers, scopes desirable

Experience working with AMD 64 architecture a great plus

Experience working with PCI-Express a plus

System level knowledge a must

System is defined as a test bench containing (CPU + GPU + multi-media engines + Southbridge) with hardware based coherency, hardware based transaction ordering

System could be a simulation test bench, emulation test bench or a board

System level knowledge/verification does not mean signal integrity checking, electrical checks, EMC checks, thermal checks, ATPG testing on a board, DFT/DFx testing, static timing analysis, lint checking

Tests will be written in C/C++, compiled for CPU and will be run on simulation/emulation/board unchanged

Block/unit level verification skills using OVM/UVM knowledge desirable (not required for the work, but having this knowledge means the candidate has been working on verification in the recent past).

Good communication and interpersonal skills to work with different teams to drive the defects to closure

Familiarity with Agile, or experience working in an Agile environment

Able to interact with multiple stake holders



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